Senior Software Developer

Job Description

About the Role

As a Senior Digital Design Engineer you will be working to implement high performance AI inference solutions on FPGA. You will contribute to our IP library in SystemVerilog and build out complete FPGA design solutions for customers. You will work as part of our diverse team of developers and researchers, on IP that is core to our inference products. You will use your experience to deliver highly performant, well tested and extensible code for some of the most widely deployed AI in modern data centers. You will work closely with our software and machine learning engineers, integrating against Myrtle’s compiler/runtime/driver stack, to build high-reliability, low-latency, and high-throughput inference applications.

You will work with the latest AI capable FPGAs from multiple FPGA vendors to develop RTL in SystemVerilog. You will generate maintainable and parameterizable IP components, to enable reuse across multiple FPGAs and applications. You will package IP into full solution implementations, achieve timing closure through floorplanning and test solutions on the board. You will make low level software interface code changes to support integration with our software stacks. You will work in a Linux development environment.

You will help to define the ways of working in the FPGA team, including coding standards and test. You will help the team to plan activities using Agile scrum methodology.

What we do

Myrtle.ai does the engineering to make deep learning a low power, high performance reality today. Focusing on reducing the power consumption of the world’s data centers, we strive to use our expertise to transform the world today by making tomorrow’s AI inference workloads run with unsurpassed efficiency. We’re a team of engineers and scientists with deep technical expertise who love a technical challenge in a friendly collaborative environment. We focus on end to end problem optimisation, starting at the algorithm and adapting the whole stack to get world leading performance from today’s silicon solutions.

Culture

We are a small friendly team, who work with some of the biggest problems in ML today. We strive for excellent technical performance in an environment where everyone contributes directly to the company’s success. We are collaborative and multi-disciplined, welcoming innovation and critical thinking from everyone.

We are based in central Cambridge UK, and enjoy sharing food and games. We are currently running a hybrid working scheme with minimum 3 days on site, allowing a degree of home working. We can accommodate other non standard working patterns for staff with particular requirements.

Myrtle is an equal opportunity employer. We value diversity at our company and are committed to creating an inclusive environment for all employees, providing equal opportunities to all persons without discrimination. We recognize the excellent benefits in having a diverse workforce from different backgrounds and employ solely on ability.

How to Apply

Email your CV to [email protected]

What you will be doing

• Writing and testing IP components in SystemVerilog for FPGA
• Building full applications for FPGA using our IP library
• Integrating with third party IP for external memory PCIe subsystems
• Extending IP verification code and integrating into automated test environments
• Working with software interface routines to support FPGA integration into the software stacks
• Learning about a range of Machine Learning inference optimization techniques
• Providing technical support for customer engagements

We're excited if you have

• At least 5 years experience generating clear, well-documented, and well-tested SystemVerilog, Verilog or VHDL code
• Masters degree in Engineering, Mathematics or other Scientific Discipline
• Worked with FPGA EDA tools such as Quartus or Vivado
• Worked with software languages such as C, C++, Python
• Familiarity with Linux development environments, version control and CI systems
• Experience of bringing up full FPGA designs and debugging on hardware
• Experience optimising RTL designs to achieve timing closure
• Good verbal and written communication skills
• [Nice to have] Familiarity with neural network architectures
• [Nice to have] Interest in Functional Programming Languages